This invention relates to low-power-dissipation circuits and, more particularly, to low-power-dissipation circuits fabricated in integrated-circuit form utilizing complementary metal-oxide-semiconductor (CMOS) technology.
It is known that low power dissipation in a conventional CMOS circuit can be achieved if the power supply lead of the circuit is ramped repetitively between VDD and VSS. During the so-called power-down phase of each ramped cycle, the state of the circuit is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (pulsed power supply) CMOS and is characterized by a power dissipation property that is typically approximately an order of magnitude less than that of conventional CMOS circuits powered by a fixed-value power supply. The technique is described in "Pulsed Power Supply CMOS - PPS CMOS" by T. J. Gabara, Proceedings of 1994 Symposium on Low Power Electronics, pages 98-99. Further, the technique is described in T. J. Gabara's copending commonly assigned U.S. patent application designated Ser. No. 08/225,950, filed Apr. 8, 1994.
Reliable low-power operation of PPS circuits on a chip requires accurate clock signals that are consistently synchronous with the occurrence of the pulsed power supply waveform. The clock signals are utilized to synchronize data flow on the chip. In particular, the clock signals are employed to control the operation of all clocked PPS circuits such as PPS latches and flip-flops. Also, clock signals are needed on the chip to time the operation of conventional CMOS latches and flip-flops. And, for controlling the operation of both conventional and PPS master/slave-type latches, complementary clock signals are required.
In practice, the generation of clock signals that have a prescribed waveform and that are synchronous with PPS signals, and that remain so over time, is a challenging task. This is particularly true if during operation of a chip the characteristics of the PPS waveform should change. And if the clock and PPS signals do, for whatever reason, fall out of phase, the advantageous low-power properties of the PPS circuits are thereby deleteriously affected.
Additionally, the transmission of data signals between chips is another area in which considerations of power dissipation in CMOS circuits are extremely important. This is so due to the fact that the interconnections between chips typically exhibit a high-capacitance characteristic. Hence, conventional CMOS driver circuits utilized to propagate signals from one chip to another inevitably consume an undesirably large amount of power.